As the nearing end of CMOS scaling will cap chip transistor budgets, optimization will eventually deliver diminishing returns, and eccelerators will reach a limit of near-optimal compute and hardware co-optimization. We term this limit the accelerator wall. [0]

[0] Adi Fuchs and David Wentzlaff, “The Accelerator Wall: Limits of Chip-Specialization”, In Proceedings of the 25th IEEE International Symposium on High-Performance Computer Architecture (HPCA ‘19), February 2019. Best Paper Award Nominee.